1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly to a semiconductor memory device including a circuit executing testing for reliability evaluation.
2. Description of the Background Art
Recently, attention is focused on logic-embedded devices having various logic circuits incorporated on one chip. These logic-embedded devices generally have a structure in which various types of transistors are employed according to the function and application. Specifically, from the standpoint of high speed operation and power consumption, two types of transistors differing in the thickness of the oxide film are embedded in the circuit. For example, with regards to a data readout operation of data stored in a memory array, a thin film transistor is employed for a sense amplifier that requires high speed operation whereas a thick film transistor for applying boosted voltage is employed for an access transistor to access a selected memory cell.
The reliability testing of a device will be described hereinafter. In general, failure of a device is mainly divided into three periods, i.e., the initial failure period, the incidental failure period, and the wear failure period over time. Initial failure occurs immediately at the start of usage, representing any defect of the device fabrication. Most of the defects related to margin belong to this type. Such failure rapidly decreases over time. Then, the incidental failure period follows during which a low failure rate is exhibited continuously over a long constant period of time. Then, the failure rate suddenly increases as the device approaches its durable term (wear failure period). It is desirable that the device is used within the incidental failure period. This period corresponds to the lifetime. Therefore, the need arises for a device that has a low and constant incidental failure rate and a long incidental failure period in order to improve the reliability of the device.
For the purpose of removing any initial failure in advance, screening to remove defective products must be carried out by subjecting the device to an acceleration operation aging for a predetermined period of time. In order to effectively conduct such screening in a short period of time, it is desirable that the initial failure rate rapidly decreases over time to expedite entering the incidental failure period. One generally known screening method is the high temperature operation test (burn-in testing). A wafer level burn-in testing that is conducted in a wafer state is particularly effective. This method allows the dielectric film of a transistor or the like to be directly evaluated actually using a device. Various factors of failures such as interconnection shorting can be rapidly elicited by applying high temperature and high electric field stress. Japanese Patent Laying-Open No. 2001-250398 discloses a structure to execute burn-in testing on a wafer level using a precharge voltage supply line to precharge a bit line in a memory array.
However, the problem of the thin film transistor being destroyed if a voltage for burn-in testing corresponding to a thick film transistor is applied to a thin film transistor is associated with the logic-embedded devices incorporating the aforementioned two different types of transistors.
In view of the foregoing, an object of the present invention is to provide a semiconductor memory device that allows execution of burn-in testing effectively in a logic-embedded device and the like.
According to an aspect of the present invention, a semiconductor memory device includes a plurality of memory cells having charge stored corresponding to storage data, a bit line, a peripheral circuit, an isolation unit, first and second voltage supply lines, and a voltage control circuit. A bit line is connected to a selected memory cell among the plurality of memory cells in a data readout mode. The peripheral circuit is connected to a bit line in a data readout mode to execute data reading with respect to the selected memory cell. The isolation unit electrically isolates the bit line into first and second regions of a bit line corresponding to the plurality of memory cells and the peripheral circuit, respectively, as necessary. The first voltage supply line is provided corresponding to the bit line in the first region. The second voltage supply line is provided corresponding to the bit line in the second region. The voltage control circuit controls the voltage to be supplied to the first and second voltage supply lines. The voltage control circuit supplies the same voltage to the first and second voltage supply lines in an operation mode, and supplies different voltages to the first and second voltage supply lines in a test mode.
The bit lines are isolated into the first and second regions, and each region corresponds to a different voltage supply line. The voltage control circuit supplies the same voltage in an operation mode and different voltages in a test mode to the first and second voltage supply lines. Therefore, a voltage corresponding to one and the other of the regions can be supplied from a corresponding voltage supply line in a test mode. Thus, test voltage can be applied in an efficient manner.
According to another aspect of the present invention, a semiconductor memory device includes a memory cell storing charge corresponding to storage data, a bit line, a voltage supply line, and a voltage control circuit. The bit line transmits a voltage of a level corresponding to the storage data in a memory cell in a data readout mode. The voltage supply line supplies a cell plate voltage to the memory cell. The memory cell includes an access transistor and a capacitor. The access transistor provided between a storage node and a bit line is turned on in a data readout mode. The capacitor provided between the storage node and the voltage supply line retains charge. In a test mode, the access transistor is turned off. The voltage control circuit supplies different voltages respectively to the voltage supply line and bit line in a test mode.
According to the above-described structure, testing can be conducted with stress applied between the bit line and voltage supply line without applying high stress on the capacitor to identify any defect between signal lines.